RiscvSpecFormal
sifive
The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
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8 data points · 2021-07-01 → 2026-04-01How do you feel about this project?
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Question copied to clipboardWhat is the sifive/RiscvSpecFormal GitHub project? Description: "The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.". Written in Haskell. Explain what it does, its main use cases, key features, and who would benefit from using it.
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