RiscvSpecFormal

hardware

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

How to download and setup RiscvSpecFormal

Open terminal and run command

git clone https://github.com/sifive/RiscvSpecFormal.git

git clone is used to create a copy or clone of RiscvSpecFormal repositories. You pass git clone a repository URL.
it supports a few different network protocols and corresponding URL formats.

Also you may download zip file with RiscvSpecFormal https://github.com/sifive/RiscvSpecFormal/archive/master.zip

Or simply clone RiscvSpecFormal with SSH

[email protected]:sifive/RiscvSpecFormal.git

If you have some problems with RiscvSpecFormal

You may open issue on RiscvSpecFormal support forum (system) here: https://github.com/sifive/RiscvSpecFormal/issues

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