FPGA-SystolicArray

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

hardware

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29 Stars

6 Forks

2 Watchers

SystemVerilog Language

80.8 SrcLog Score

Cost to Build

$73.2K

Market Value

$82.6K

How is this calculated?

Growth over time

5 data points · 2026-07-19 → 2026-10-11

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What is the dsa-shua/FPGA-SystolicArray GitHub project? Description: "Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis". Written in SystemVerilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

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git clone https://github.com/dsa-shua/FPGA-SystolicArray.git

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[email protected]:dsa-shua/FPGA-SystolicArray.git

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Download main.zip

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