FPGA_RealTime_and_Static_Sobel_Edge_Detection

AngeloJacobo

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

real-time

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68 Stars

7 Forks

68 Watchers

Verilog Language

mit License

100 SrcLog Score

Cost to Build

$5.7K

Market Value

$8.4K

How is this calculated?

Growth over time

7 data points · 2021-11-01 → 2026-04-01

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What is the AngeloJacobo/FPGA_RealTime_and_Static_Sobel_Edge_Detection GitHub project? Description: "Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images". Written in Verilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone FPGA_RealTime_and_Static_Sobel_Edge_Detection

Clone via HTTPS

git clone https://github.com/AngeloJacobo/FPGA_RealTime_and_Static_Sobel_Edge_Detection.git

Clone via SSH

[email protected]:AngeloJacobo/FPGA_RealTime_and_Static_Sobel_Edge_Detection.git

Download ZIP

Download master.zip

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