Mersenne-twister-hardware
jeudine
A flexible hardware module written in SystemVerilog which implements the Mersene twister (using a 32-bit word length). A simulation and a test bench written in SystemC, which uses Verilator were created in order to verify the correctness and to measure performance of the hardware module.
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4 data points · 2021-07-30 → 2022-03-23How do you feel about this project?
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Question copied to clipboardWhat is the jeudine/Mersenne-twister-hardware GitHub project? Description: "A flexible hardware module written in SystemVerilog which implements the Mersene twister (using a 32-bit word length). A simulation and a test bench written in SystemC, which uses Verilator were created in order to verify the correctness and to measure performance of the hardware module.". Written in C++. Explain what it does, its main use cases, key features, and who would benefit from using it.
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