Pyverilog

PyHDI

Python-based Hardware Design Processing Toolkit for Verilog HDL

hardware parser compiler

View on GitHub

783 Stars

212 Forks

783 Watchers

Python Language

apache-2.0 License

100 SrcLog Score

Cost to Build

$56.3K

Market Value

$176.7K

How is this calculated?

Growth over time

18 data points · 2021-07-01 → 2026-04-01

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What is the PyHDI/Pyverilog GitHub project? Description: "Python-based Hardware Design Processing Toolkit for Verilog HDL". Written in Python. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone Pyverilog

Clone via HTTPS

git clone https://github.com/PyHDI/Pyverilog.git

Clone via SSH

[email protected]:PyHDI/Pyverilog.git

Download ZIP

Download master.zip

Found an issue?

Report bugs or request features on the Pyverilog issue tracker:

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