Reduceron
FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
How to download and setup Reduceron
Open terminal and run command
git clone https://github.com/tommythorn/Reduceron.git
git clone is used to create a copy or clone of Reduceron repositories.
You pass git clone a repository URL. it supports a few different network protocols and corresponding URL formats.
Also you may download zip file with Reduceron https://github.com/tommythorn/Reduceron/archive/master.zip
Or simply clone Reduceron with SSH
[email protected]:tommythorn/Reduceron.git
If you have some problems with Reduceron
You may open issue on Reduceron support forum (system) here: https://github.com/tommythorn/Reduceron/issuesSimilar to Reduceron repositories
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