Alarm-Clock

Alarm-Clock

AkhilRai28

This project implements a fully functional digital alarm clock using Verilog and Vivado. The design includes features such as setting the time, alarm functionality, and real-time clock display. The project simulates clock timing and alarm triggers, with testbenches for verifying accuracy and reliability on FPGA.

2 Stars
0 Forks
2 Watchers
VHDL Language
Cost to Build
$4.6K
Market Value
$2.1K

Growth over time

1 data points  ·  2025-08-29 → 2025-08-29
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What is the AkhilRai28/Alarm-Clock GitHub project? Description: "This project implements a fully functional digital alarm clock using Verilog and Vivado. The design includes features such as setting the time, alarm functionality, and real-time clock display. The project simulates clock timing and alarm triggers, with testbenches for verifying accuracy and reliability on FPGA.". Written in VHDL. Explain what it does, its main use cases, key features, and who would benefit from using it.

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git clone https://github.com/AkhilRai28/Alarm-Clock.git

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[email protected]:AkhilRai28/Alarm-Clock.git

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Download master.zip

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