axiplasma

plasoc

AXI/MIPS SoC developed in VHDL with FreeRTOS port. Capable of running either preemptively or cooperatively.

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6 Stars

1 Forks

6 Watchers

VHDL Language

mit License

Cost to Build

$15.96M

Market Value

$10.75M

How is this calculated?

Growth over time

5 data points · 2021-08-01 → 2022-09-01

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What is the plasoc/axiplasma GitHub project? Description: "AXI/MIPS SoC developed in VHDL with FreeRTOS port. Capable of running either preemptively or cooperatively.". Written in VHDL. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone axiplasma

Clone via HTTPS

git clone https://github.com/plasoc/axiplasma.git

Clone via SSH

[email protected]:plasoc/axiplasma.git

Download ZIP

Download master.zip

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Report bugs or request features on the axiplasma issue tracker:

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