bachelor-thesis

Thesis covers research on digital signal processing with software defined radio techniques applied in FPGA environment. It is written entirely in Polish language, except english abstract

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3 Stars

1 Forks

3 Watchers

Verilog Language

Cost to Build

$24.61M

Market Value

$12.81M

How is this calculated?

Growth over time

1 data points · 2021-07-30 → 2021-07-30

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What is the lstolcman/bachelor-thesis GitHub project? Description: "Thesis covers research on digital signal processing with software defined radio techniques applied in FPGA environment. It is written entirely in Polish language, except english abstract". Written in Verilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone bachelor-thesis

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git clone https://github.com/lstolcman/bachelor-thesis.git

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[email protected]:lstolcman/bachelor-thesis.git

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Download master.zip

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