bedrock-rtl

xlsynth

High quality and composable RTL libraries in SystemVerilog

hardware

View on GitHub

32 Stars

5 Forks

32 Watchers

SystemVerilog Language

apache-2.0 License

100 SrcLog Score

Cost to Build

$175.8K

Market Value

$395.3K

How is this calculated?

Growth over time

3 data points · 2026-04-07 → 2026-04-21

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What is the xlsynth/bedrock-rtl GitHub project? Description: "High quality and composable RTL libraries in SystemVerilog". Written in SystemVerilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone bedrock-rtl

Clone via HTTPS

git clone https://github.com/xlsynth/bedrock-rtl.git

Clone via SSH

[email protected]:xlsynth/bedrock-rtl.git

Download ZIP

Download master.zip

Found an issue?

Report bugs or request features on the bedrock-rtl issue tracker:

Open GitHub Issues

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