riscv-ooo-core

riscv-ooo-core

devtyagi3909

Full superscalar RV32I out-of-order processor with Tomasulos Algorithm, 7-stage pipeline, and UVM testbench. 1st Place + Special Jury Award — SanDisk Hardware Hackathon.

12 Stars
0 Forks
0 Watchers
Verilog Language
74.6 SrcLog Score
Cost to Build
$13.5K
Market Value
$17.8K

Growth over time

1 data points  ·  2026-09-05 → 2026-09-05
Stars Forks Watchers
💬

How do you feel about this project?

Ask AI about riscv-ooo-core

Question copied to clipboard

What is the devtyagi3909/riscv-ooo-core GitHub project? Description: "Full superscalar RV32I out-of-order processor with Tomasulos Algorithm, 7-stage pipeline, and UVM testbench. 1st Place + Special Jury Award — SanDisk Hardware Hackathon.". Written in Verilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

Question is copied to clipboard — paste it after the AI opens.

How to clone riscv-ooo-core

Clone via HTTPS

git clone https://github.com/devtyagi3909/riscv-ooo-core.git

Clone via SSH

[email protected]:devtyagi3909/riscv-ooo-core.git

Download ZIP

Download main.zip

Found an issue?

Report bugs or request features on the riscv-ooo-core issue tracker:

Open GitHub Issues