riscv_vhdl

sergeykhbr

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

View on GitHub Website

643 Stars

106 Forks

643 Watchers

Verilog Language

apache-2.0 License

Cost to Build

$10.77M

Market Value

$32.01M

How is this calculated?

Growth over time

5 data points · 2022-02-01 → 2025-03-01

Stars Forks Watchers

💬

How do you feel about this project?

Ask AI about riscv_vhdl

Question copied to clipboard

What is the sergeykhbr/riscv_vhdl GitHub project? Description: "Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators". Written in Verilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

Question is copied to clipboard — paste it after the AI opens.

How to clone riscv_vhdl

Clone via HTTPS

git clone https://github.com/sergeykhbr/riscv_vhdl.git

Clone via SSH

[email protected]:sergeykhbr/riscv_vhdl.git

Download ZIP

Download master.zip

Found an issue?

Report bugs or request features on the riscv_vhdl issue tracker:

Open GitHub Issues

Similar to riscv_vhdl

openage tiled liteide qt qutebrowser MuseScore mapbox-gl-native qTox Clementine antimony flameshot gqrx mixxx appleseed pywebview toggldesktop edb-debugger openauto CuteMarkEd LibreCAD qgroundcontrol otter-browser feedback QDarkStyleSheet stellarium hotspot GoldenCheetah SlicerGitSVNArchive qtbase nitroshare-desktop