Hardware-acceleration-of-chess-engine

Hardware-acceleration-of-chess-engine

dejangrubisic

This project makes one hardware-software co-design solution of chess engine accelerator. For design it is used VHDL, description of system SystemC and functional verification SystemVerilog

4 Stars
0 Forks
4 Watchers
HTML Language
Cost to Build
$1.50M
Market Value
$751.7K

Growth over time

4 data points  ·  2021-07-30 → 2022-03-23
Stars Forks Watchers
💬

How do you feel about this project?

Ask AI about Hardware-acceleration-of-chess-engine

Question copied to clipboard

What is the dejangrubisic/Hardware-acceleration-of-chess-engine GitHub project? Description: "This project makes one hardware-software co-design solution of chess engine accelerator. For design it is used VHDL, description of system SystemC and functional verification SystemVerilog". Written in HTML. Explain what it does, its main use cases, key features, and who would benefit from using it.

Question is copied to clipboard — paste it after the AI opens.

How to clone Hardware-acceleration-of-chess-engine

Clone via HTTPS

git clone https://github.com/dejangrubisic/Hardware-acceleration-of-chess-engine.git

Clone via SSH

[email protected]:dejangrubisic/Hardware-acceleration-of-chess-engine.git

Download ZIP

Download master.zip

Found an issue?

Report bugs or request features on the Hardware-acceleration-of-chess-engine issue tracker:

Open GitHub Issues