RISC-V-32I-5-stage-Pipeline-Core

RISC-V-32I-5-stage-Pipeline-Core

Varunkumar0610

Implementation of 5 Stage 32I RISC V Pipeline Processor.

34 Stars
6 Forks
1 Watchers
Verilog Language
81.7 SrcLog Score
Cost to Build
$60.2K
Market Value
$86.5K

Growth over time

5 data points  ·  2026-04-10 → 2026-08-09
Stars Forks Watchers
💬

How do you feel about this project?

Ask AI about RISC-V-32I-5-stage-Pipeline-Core

Question copied to clipboard

What is the Varunkumar0610/RISC-V-32I-5-stage-Pipeline-Core GitHub project? Description: "Implementation of 5 Stage 32I RISC V Pipeline Processor.". Written in Verilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

Question is copied to clipboard — paste it after the AI opens.

How to clone RISC-V-32I-5-stage-Pipeline-Core

Clone via HTTPS

git clone https://github.com/Varunkumar0610/RISC-V-32I-5-stage-Pipeline-Core.git

Clone via SSH

[email protected]:Varunkumar0610/RISC-V-32I-5-stage-Pipeline-Core.git

Download ZIP

Download main.zip

Found an issue?

Report bugs or request features on the RISC-V-32I-5-stage-Pipeline-Core issue tracker:

Open GitHub Issues