RISCV-CPU

gws8820

A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)

runtime

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5 Stars

2 Forks

5 Watchers

SystemVerilog Language

mit License

78.4 SrcLog Score

Cost to Build

$373.9K

Market Value

$465.5K

How is this calculated?

Growth over time

3 data points · 2026-04-09 → 2026-04-24

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What is the gws8820/RISCV-CPU GitHub project? Description: "A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)". Written in SystemVerilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone RISCV-CPU

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git clone https://github.com/gws8820/RISCV-CPU.git

Clone via SSH

[email protected]:gws8820/RISCV-CPU.git

Download ZIP

Download master.zip

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