RISCV-CPU

RISCV-CPU

gws8820

A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)

9 Stars
1 Forks
0 Watchers
HTML Language
mit License
64 SrcLog Score
Cost to Build
$297.4K
Market Value
$371.4K

Growth over time

7 data points  ·  2026-04-09 → 2026-09-26
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What is the gws8820/RISCV-CPU GitHub project? Description: "A 6-Stage RISC-V RV32IM Core on FPGA (263.7 CoreMark, 91.0 DMIPS@100MHz)". Written in HTML. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone RISCV-CPU

Clone via HTTPS

git clone https://github.com/gws8820/RISCV-CPU.git

Clone via SSH

[email protected]:gws8820/RISCV-CPU.git

Download ZIP

Download main.zip

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