Optimized dual AMD Strix Halo (gfx1151) vLLM MoE inference: TP=2 over USB4, tuned int4 MoE kernel, ~8us interconnect, serialized serving
What is the ayysasha/Strix-halo-dual-optimized GitHub project? Description: "Optimized dual AMD Strix Halo (gfx1151) vLLM MoE inference: TP=2 over USB4, tuned int4 MoE kernel, ~8us interconnect, serialized serving". Written in Shell. Explain what it does, its main use cases, key features, and who would benefit from using it.
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