Verilog-UART

Verilog-UART

WangXuan95

3 independent modules for FPGA: UART receiver, UART transmitter, UART interactive debugger. 3个独立模块：UART接收器、UART发送器、UART交互式调试器。

debugging
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36 Stars
4 Forks
36 Watchers
SystemVerilog Language
92.4 SrcLog Score
Cost to Build
$28.4K
Market Value
$35.1K
How is this calculated?

Growth over time

6 data points  ·  2021-08-01 → 2023-03-01
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What is the WangXuan95/Verilog-UART GitHub project? Description: "3 independent modules for FPGA: UART receiver, UART transmitter, UART interactive debugger. 3个独立模块：UART接收器、UART发送器、UART交互式调试器。". Written in SystemVerilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

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git clone https://github.com/WangXuan95/Verilog-UART.git

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[email protected]:WangXuan95/Verilog-UART.git

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