firrtl

firrtl

chipsalliance

Flexible Intermediate Representation for RTL

hardware compiler
View on GitHub Website
748 Stars
180 Forks
16 Watchers
Scala Language
apache-2.0 License
100 SrcLog Score
Cost to Build
$6.34M
Market Value
$14.79M
How is this calculated?

Growth over time

20 data points  ·  2021-07-01 → 2026-11-01
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What is the chipsalliance/firrtl GitHub project? Description: "Flexible Intermediate Representation for RTL". Written in Scala. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone firrtl

Clone via HTTPS

git clone https://github.com/chipsalliance/firrtl.git

Clone via SSH

[email protected]:chipsalliance/firrtl.git

Download ZIP

Download 1.6.x.zip

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