firrtl

chipsalliance

Flexible Intermediate Representation for RTL

hardware compiler

View on GitHub Website

749 Stars

179 Forks

749 Watchers

Scala Language

apache-2.0 License

100 SrcLog Score

Cost to Build

$6.15M

Market Value

$19.06M

How is this calculated?

Growth over time

15 data points · 2021-07-01 → 2026-04-01

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What is the chipsalliance/firrtl GitHub project? Description: "Flexible Intermediate Representation for RTL". Written in Scala. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone firrtl

Clone via HTTPS

git clone https://github.com/chipsalliance/firrtl.git

Clone via SSH

[email protected]:chipsalliance/firrtl.git

Download ZIP

Download master.zip

Found an issue?

Report bugs or request features on the firrtl issue tracker:

Open GitHub Issues

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