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Repositories (5)
chisel
chipsalliance/chisel
Scala
Chisel: A Modern Hardware Design Language
4.6k
650
rocket-chip
chipsalliance/rocket-chip
Scala
Rocket Chip Generator
3.7k
1.3k
verible
chipsalliance/verible
C++
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
1.8k
276
firrtl
chipsalliance/firrtl
Scala
Flexible Intermediate Representation for RTL
749
179
Surelog
chipsalliance/Surelog
C++
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
457
79