Repositories (9)
Complete end-to-end FPGA trading system: hardware acceleration (<5μs latency), kernel bypass (AF_XDP, DPDK), automated market maker, FIX 4.2 execution engine. 35 projects from Ethernet PHY to multi-platform apps. Real NASDAQ ITCH validation (563K+ samples). Production-grade low-latency architecture. LLM-Inference
Vivado 2025.2 block design for VD100 (XCVE2302) — CIPS, NoC, AIE-ML, AXI interrupt controller, MyLEDIP. Reusable hardware platform for Vitis AIE kernel projects. Exports XSA for vd100_platform. No VCK190 required.
Yocto Scarthgap meta layer for VD100 (XCVE2302) — XRT 2025.2, zocl, AIE-ML pipeline. Fixes undocumented BOOT.BIN CDO gap that leaves all AIE tiles clock-gated under Linux. Submodule of versal-ai-edge-vd100-linux.
First documented end-to-end PL + AIE-ML + PS pipeline on Versal AI Edge XCVE2302 (VD100). MA crossover trading signal via HLS DMA + AIE graph + XRT host app. No VCK190. No MATLAB. Ethereum audit log on Hardhat.
Vitis 2025.2 system project for VD100 (XCVE2302) — v++ link + package for AIE-ML v2 + HLS kernel integration. Produces aie.xclbin and BOOT.BIN CDO artifacts. Reusable: swap AIE kernel or add HLS kernels without new project.
AIE-ML moving average crossover kernel for VD100 (XCVE2302). Dual MA (fast 10 / slow 50 period), BUY/SELL/HOLD signal. 56 int32 samples/iteration via HLS DMA. Used in vd100-aie-pipeline. Vitis 2025.2.
Post-link Vitis pipeline platform for VD100 (XCVE2302). Add new HLS or AIE kernels to the existing Vitis region without starting a new Vivado project. Built from vd100_ma_system_project post-link XSA.
PS userspace XRT application for the VD100 MA Crossover AIE-ML pipeline. Drives mm2s/s2mm HLS kernels and mygraph via XRT 2025.2 on XCVE2302. Includes golden test vector validation and XRT lifecycle performance analysis.
Vitis 2025.2 extensible platform for VD100 (XCVE2302) built from vd100_bd_aie_pipeline XSA. Reusable target for AIE kernel compilation and v++ link. Linux A72 domain. No VCK190 required.