vd100_bd_aie_pipeline

vd100_bd_aie_pipeline

adilsondias-engineer

Vivado 2025.2 block design for VD100 (XCVE2302) — CIPS, NoC, AIE-ML, AXI interrupt controller, MyLEDIP. Reusable hardware platform for Vitis AIE kernel projects. Exports XSA for vd100_platform. No VCK190 required.

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VHDL Language
apache-2.0 License
30 SrcLog Score
Cost to Build
$148.8K
Market Value
$17.9K

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1 data points  ·  2026-04-18 → 2026-04-18
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What is the adilsondias-engineer/vd100_bd_aie_pipeline GitHub project? Description: "Vivado 2025.2 block design for VD100 (XCVE2302) — CIPS, NoC, AIE-ML, AXI interrupt controller, MyLEDIP. Reusable hardware platform for Vitis AIE kernel projects. Exports XSA for vd100_platform. No VCK190 required.". Written in VHDL. Explain what it does, its main use cases, key features, and who would benefit from using it.

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