sifive

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)

Kami based processor implementations and specifications