DaCe - Data Centric Parallel Programming
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
Neural Code Comprehension: A Learnable Representation of Code Semantics
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing
A Data-Centric Compiler for Machine Learning
SeBS: serverless benchmarking suite for automatic performance analysis of FaaS platforms.
development repository for the open earth compiler
FPGA acceleration of arbitrary precision floating point computations.
Implementation of the N^2-formulation of N-body simulation with Vivado HLS for SDAccel platforms.
Implementation of time and space-tiled stencil in Vivado HLS.