iir-audio-filter-fpga

Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA

filter

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12 Stars

2 Forks

12 Watchers

VHDL Language

mit License

95.2 SrcLog Score

Cost to Build

$199.7K

Market Value

$177.9K

How is this calculated?

Growth over time

7 data points · 2021-08-01 → 2026-04-01

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What is the gabrielebaris/iir-audio-filter-fpga GitHub project? Description: "Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA". Written in VHDL. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone iir-audio-filter-fpga

Clone via HTTPS

git clone https://github.com/gabrielebaris/iir-audio-filter-fpga.git

Clone via SSH

[email protected]:gabrielebaris/iir-audio-filter-fpga.git

Download ZIP

Download master.zip

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