verilog-vcd-parser

verilog-vcd-parser

ben-marshall

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

parser
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103 Stars
39 Forks
103 Watchers
C++ Language
mit License
100 SrcLog Score
Cost to Build
$7.2K
Market Value
$12.7K
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Growth over time

8 data points  ·  2021-08-01 → 2026-04-01
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What is the ben-marshall/verilog-vcd-parser GitHub project? Description: "A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.". Written in C++. Explain what it does, its main use cases, key features, and who would benefit from using it.

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git clone https://github.com/ben-marshall/verilog-vcd-parser.git

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Download master.zip

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