Surelog
chipsalliance
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
272
Stars
63
Forks
272
Watchers
C++
Language
apache-2.0
License
Growth over time
7 data points · 2021-08-01 → 2023-05-01
Stars
Forks
Watchers
💬
How do you feel about this project?
Ask AI about Surelog
Question copied to clipboardWhat is the chipsalliance/Surelog GitHub project? Description: "SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX ". Written in C++. Explain what it does, its main use cases, key features, and who would benefit from using it.
Question is copied to clipboard — paste it after the AI opens.
How to clone Surelog
Clone via HTTPS
git clone https://github.com/chipsalliance/Surelog.git
Clone via SSH
[email protected]:chipsalliance/Surelog.git
Download ZIP
Download master.zipFound an issue?
Report bugs or request features on the Surelog issue tracker:
Open GitHub Issues