async_fifo

dpretet

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

async

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370 Stars

88 Forks

370 Watchers

Verilog Language

other License

Cost to Build

$77.4K

Market Value

$256.1K

How is this calculated?

Growth over time

2 data points · 2023-04-01 → 2025-08-01

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What is the dpretet/async_fifo GitHub project? Description: "A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog". Written in Verilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone async_fifo

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git clone https://github.com/dpretet/async_fifo.git

Clone via SSH

[email protected]:dpretet/async_fifo.git

Download ZIP

Download master.zip

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