3 Stars
0 Forks
5 Watchers
Verilog Language
31.9 SrcLog Score
Cost to Build
$286.4K
Market Value
$130.4K

Growth over time

10 data points  ·  2021-08-01 → 2026-08-01
Stars Forks Watchers
💬

How do you feel about this project?

Ask AI about csp-hls

Question copied to clipboard

What is the ucb-hls/csp-hls GitHub project? Written in Verilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

Question is copied to clipboard — paste it after the AI opens.

How to clone csp-hls

Clone via HTTPS

git clone https://github.com/ucb-hls/csp-hls.git

Clone via SSH

[email protected]:ucb-hls/csp-hls.git

Download ZIP

Download master.zip

Found an issue?

Report bugs or request features on the csp-hls issue tracker:

Open GitHub Issues