zslwyuan

zslwyuan

👤 Developer

6 repositories on SrcLog

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6 Repos
67 Stars
21 Forks
67 Watchers

Repositories (6)

Hi-DMM zslwyuan/Hi-DMM VHDL

Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)

25
Zynq_HLS_DDR_Dataflow_kernel_2mm zslwyuan/Zynq_HLS_DDR_Dataflow_kernel_2mm VHDL

This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation

21
High-Performance-Karatsuba-Multiplier-HLS-FPGA zslwyuan/High-Performance-Karatsuba-Multiplier-HLS-FPGA Ada

Implement High-Performance Karatsuba Multiplier in High-Level Synthesis (HLS) for FPGA Based on Recursive Template

9
Zedboard_Intergrating_HLS_IP_AND_DDR zslwyuan/Zedboard_Intergrating_HLS_IP_AND_DDR VHDL

This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.

7
Zynq_HLS_DDR_AXI_IPs_Multiple_Clock zslwyuan/Zynq_HLS_DDR_AXI_IPs_Multiple_Clock VHDL
3
Hi-ClockFlow zslwyuan/Hi-ClockFlow

Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis

2