Zedboard_Intergrating_HLS_IP_AND_DDR

This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.

hls

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7 Stars

4 Forks

7 Watchers

VHDL Language

Cost to Build

$5.01M

Market Value

$5.12M

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7 data points · 2021-08-01 → 2025-04-01

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What is the zslwyuan/Zedboard_Intergrating_HLS_IP_AND_DDR GitHub project? Description: "This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.". Written in VHDL. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone Zedboard_Intergrating_HLS_IP_AND_DDR

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git clone https://github.com/zslwyuan/Zedboard_Intergrating_HLS_IP_AND_DDR.git

Clone via SSH

[email protected]:zslwyuan/Zedboard_Intergrating_HLS_IP_AND_DDR.git

Download ZIP

Download master.zip

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