Zedboard_Intergrating_HLS_IP_AND_DDR

hls

This is a project integrating HLS IP and CortexA9 on Zynq. This project implements DDR3 random access with HLS. The Cortex A9 will print the result via UART.

How to download and setup Zedboard_Intergrating_HLS_IP_AND_DDR

Open terminal and run command

git clone https://github.com/zslwyuan/Zedboard_Intergrating_HLS_IP_AND_DDR.git

git clone is used to create a copy or clone of Zedboard_Intergrating_HLS_IP_AND_DDR repositories. You pass git clone a repository URL.
it supports a few different network protocols and corresponding URL formats.

Also you may download zip file with Zedboard_Intergrating_HLS_IP_AND_DDR https://github.com/zslwyuan/Zedboard_Intergrating_HLS_IP_AND_DDR/archive/master.zip

Or simply clone Zedboard_Intergrating_HLS_IP_AND_DDR with SSH

[email protected]:zslwyuan/Zedboard_Intergrating_HLS_IP_AND_DDR.git

If you have some problems with Zedboard_Intergrating_HLS_IP_AND_DDR

You may open issue on Zedboard_Intergrating_HLS_IP_AND_DDR support forum (system) here: https://github.com/zslwyuan/Zedboard_Intergrating_HLS_IP_AND_DDR/issues

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