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Zynq_HLS_DDR_Dataflow_kernel_2mm

This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation

How to download and setup Zynq_HLS_DDR_Dataflow_kernel_2mm

Open terminal and run command
git clone https://github.com/zslwyuan/Zynq_HLS_DDR_Dataflow_kernel_2mm.git
git clone is used to create a copy or clone of Zynq_HLS_DDR_Dataflow_kernel_2mm repositories. You pass git clone a repository URL.
it supports a few different network protocols and corresponding URL formats.

Also you may download zip file with Zynq_HLS_DDR_Dataflow_kernel_2mm https://github.com/zslwyuan/Zynq_HLS_DDR_Dataflow_kernel_2mm/archive/master.zip

Or simply clone Zynq_HLS_DDR_Dataflow_kernel_2mm with SSH
[email protected]:zslwyuan/Zynq_HLS_DDR_Dataflow_kernel_2mm.git

If you have some problems with Zynq_HLS_DDR_Dataflow_kernel_2mm

You may open issue on Zynq_HLS_DDR_Dataflow_kernel_2mm support forum (system) here: https://github.com/zslwyuan/Zynq_HLS_DDR_Dataflow_kernel_2mm/issues

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