Zynq_HLS_DDR_Dataflow_kernel_2mm
zslwyuan
This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation
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7 data points · 2021-08-01 → 2025-04-01How do you feel about this project?
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Question copied to clipboardWhat is the zslwyuan/Zynq_HLS_DDR_Dataflow_kernel_2mm GitHub project? Description: "This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation". Written in VHDL. Explain what it does, its main use cases, key features, and who would benefit from using it.
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