ssr-multistage-decimator

Hardware design and FPGA-based implementation of a super sample rate multistage decimator using Vitis High-Level Synthesis.

hls

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2 Stars

1 Forks

2 Watchers

C++ Language

gpl-3.0 License

Cost to Build

$56.5K

Market Value

$31.2K

How is this calculated?

Growth over time

1 data points · 2025-04-05 → 2025-04-05

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What is the marcopausini/ssr-multistage-decimator GitHub project? Description: "Hardware design and FPGA-based implementation of a super sample rate multistage decimator using Vitis High-Level Synthesis.". Written in C++. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone ssr-multistage-decimator

Clone via HTTPS

git clone https://github.com/marcopausini/ssr-multistage-decimator.git

Clone via SSH

[email protected]:marcopausini/ssr-multistage-decimator.git

Download ZIP

Download master.zip

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