verible

chipsalliance

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

parser style-linter productivity

View on GitHub Website

1.8k Stars

276 Forks

1.8k Watchers

C++ Language

other License

100 SrcLog Score

Cost to Build

$1.35M

Market Value

$6.85M

How is this calculated?

Growth over time

9 data points · 2021-08-01 → 2026-04-01

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What is the chipsalliance/verible GitHub project? Description: "Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server". Written in C++. Explain what it does, its main use cases, key features, and who would benefit from using it.

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How to clone verible

Clone via HTTPS

git clone https://github.com/chipsalliance/verible.git

Clone via SSH

[email protected]:chipsalliance/verible.git

Download ZIP

Download master.zip

Found an issue?

Report bugs or request features on the verible issue tracker:

Open GitHub Issues

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