basic_rv32s

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

computer-science

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67 Stars

7 Forks

67 Watchers

Verilog Language

mit License

100 SrcLog Score

Cost to Build

$9.55M

Market Value

$23.21M

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Growth over time

3 data points · 2026-04-10 → 2026-04-25

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What is the RISC-KC/basic_rv32s GitHub project? Description: "🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.". Written in Verilog. Explain what it does, its main use cases, key features, and who would benefit from using it.

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