Systolic array-based Matrix Profile Computation implemented in Vitis™ HLS for Xilinx FPGAs.
What is the jlscheerer/matrix-profile-hls GitHub project? Description: "Systolic array-based Matrix Profile Computation implemented in Vitis™ HLS for Xilinx FPGAs.". Written in C++. Explain what it does, its main use cases, key features, and who would benefit from using it.
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